View EMBEDDEDPENTIUM100_2897988.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

embedded pentium ? processor 100 mhz, 133 mhz, 166 mhz datasheet product features the embedded pentium ? processor provides high performance for embedded applications. the pentium processor is compatible with the entire installed base of applications for dos*, windows*, os/2*, and unix*. the pentium processor superscalar architecture can execute two instructions per clock cycle. branch prediction and separate code and data caches also increase performance. the pipelined floating-point unit delivers a high level of performance. separate code and data caches reduce cache conflicts while remaining software transparent. the pentium processor has 3.3 million transistors and is built on intels advanced 3.3 v bicmos silicon technology. the pentium processor has on-chip dual processing support, a local multiprocessor interrupt controller, and sl power management features. n compatible with large software base ms-dos*, windows*, os/2*, unix* n 32-bit processor with 64-bit data bus n superscalar architecture two pipelined integer units are capable of two instructions/clock pipelined floating-point unit n separate code and data caches 8-kbyte code, 8-kbyte write-back data mesi cache protocol n advanced design features branch prediction virtual mode extensions n 3.3 v bicmos silicon technology n 4-mbyte pages for increased tlb hit rate n ieee 1149.1 boundary scan n dual processing configuration n functional redundancy checking support n internal error detection features n multiprocessor support multiprocessor instructions support for second-level cache n on-chip local apic controller multiprocessor interrupt management 8259 compatible n power management features system management mode clock control n fractional bus operation 166-mhz core/66-mhz bus 133-mhz core/66-mhz bus 100-mhz core/66-mhz bus n icomp ? index 2.0 rating ? 127 at 166 mhz 111 at 133 mhz 90 at 100 mhz ? contact intel corporation for more information about icomp ? index 2.0 ratings. order number: 273202-001 november 1998
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? processor may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1993, 1996, 1997, 1998 *third-party brands and names are the property of their respective owners.
datasheet 3 embedded pentium ? processor contents 1.0 architecture overview ............................................................................................. 7 1.1 pentium ? processor family architecture .............................................................. 8 1.2 pentium ? processors with voltage reduction technology.................................10 2.0 packaging information ...........................................................................................11 2.1 pentium ? processor pinout.................................................................................11 2.1.1 pin cross reference ..............................................................................13 2.1.2 design notes..........................................................................................15 2.1.3 pin quick reference ..............................................................................15 2.1.4 pin reference tables.............................................................................21 2.1.5 pin grouping according to function.......................................................24 2.2 mechanical specifications ...................................................................................25 2.3 thermal specifications ........................................................................................26 2.3.1 measuring thermal values ....................................................................26 2.3.2 thermal equations and data .................................................................27 3.0 electrical specifications ........................................................................................29 3.1 3.3 v power supply.............................................................................................29 3.2 3.3 v inputs and outputs.....................................................................................29 3.3 absolute maximum ratings.................................................................................29 3.4 dc specifications ................................................................................................30 3.5 ac specifications ................................................................................................31 3.5.1 private bus .............................................................................................31 3.5.2 power and ground .................................................................................31 3.5.3 decoupling recommendations ..............................................................32 3.5.4 connection specifications ......................................................................32 3.5.5 ac timing tables...................................................................................32
embedded pentium ? processor 4 datasheet figures 1 embedded pentium ? processor block diagram ................................................... 9 2pentium ? processor spga package pinout (top side view) ............................ 11 3pentium ? processor spga package pinout (pin side view) ............................. 12 4 spga package dimensions ............................................................................... 25 5 technique for measuring case temperature (t c ).............................................. 27 6 clock waveform.................................................................................................. 38 7 valid delay timings ............................................................................................ 38 8 float delay timings ............................................................................................ 38 9 setup and hold timings...................................................................................... 39 10 reset and configuration timings........................................................................ 39 11 test timings........................................................................................................ 40 12 test reset timings ............................................................................................. 40 13 50% v cc measurement of flight time................................................................ 41 tables 1 pin cross-reference by pin name address and data pins ........................... 13 2 pin cross-reference by pin name control pins ............................................ 14 3 pin cross-reference by pin name power, ground and no connect pins .... 15 4 pin quick reference ......................................................................................... 16 5 bus frequency selections .................................................................................. 21 6 output pins ......................................................................................................... 21 7 input pins ............................................................................................................ 22 8 input/output pins ................................................................................................ 23 9 inter-processor input/output pins ....................................................................... 23 10 pin functional grouping...................................................................................... 24 11 package information summary for pentium ? processor .................................... 25 12 spga package dimensions key ........................................................................ 25 13 power dissipation requirements for thermal solution design .......................... 26 14 thermal resistances for embedded pentium ? processors................................ 28 15 absolute maximum ratings ................................................................................ 30 16 3.3 v dc specifications ...................................................................................... 30 17 3.3 v (5 v-safe) dc specifications ..................................................................... 30 18 input and output characteristics......................................................................... 31 19 ac specifications ................................................................................................ 33 20 dual processor mode ac specifications ............................................................ 36 21 notes for tables 19 and 20................................................................................. 37
datasheet 5 embedded pentium ? processor revision history date revision description 11/12/98 001 this is the first publication of this document.

embedded pentium ? processor datasheet 7 1.0 architecture overview the intel ? embedded pentium ? processor is binary compatible with the 8086/88, 80286, intel386? dx, intel386 sx, intel486? dx, intel486 sx, inteldx2?, inteldx4? and 60/66 mhz pentium processors. the embedded pentium processor family consists of the following products: ? embedded pentium processors (described in this document). pentium processor at 166 mhz, icomp index 2.0 rating = 127 pentium processor at 133 mhz, icomp index 2.0 rating = 111 pentium processor at 100 mhz, icomp index 2.0 rating = 90 ? pentium processor with voltage reduction technology (described in a separate datasheet, order number 273203). pentium processor with voltage reduction technology at 133 mhz, icomp index 2.0 rating = 111 pentium processor features include: ? superscalar architecture ? dynamic branch prediction ? pipelined floating-point unit ? improved instruction execution time ? separate 8-kbyte code and 8-kbyte data caches ? writeback mesi protocol in the data cache ? 64-bit data bus ? bus cycle pipelining ? address parity ? internal parity checking ? functional redundancy checking ? execution tracing ? performance monitoring ? ieee 1149.1 boundary scan ? system management mode ? virtual mode extensions ? fractional bus operation allowing higher core frequency operation ? dual processing support ? sl power management features ? on-chip local apic device
embedded pentium ? processor 8 datasheet 1.1 pentium ? processor family architecture the application instruction set of the pentium processor family includes the complete intel486 processor family instruction set with extensions to accommodate some of the additional functionality of the pentium processor. all application software written for the intel386 and intel486 family microprocessors runs on pentium processors without modification. the on-chip memory management unit is completely compatible with the intel386 family and intel486 family of processors. pentium processors implement several enhancements to increase performance. the two instruction pipelines and the floating-point unit are capable of independent operation. each pipeline issues frequently used instructions in a single clock. together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. branch prediction is implemented in pentium processors. to support this, the processor has two prefetch buffers: one prefetches code in a linear fashion and the other prefetches code according to the btb so the needed code is almost always prefetched before it is needed for execution. the floating-point unit (fpu) is up to ten times faster than the fpu used on the intel486 processor for common operations including add, multiply, and load. pentium processors include separate code and data caches integrated on-chip to meet performance goals. each cache is 8 kbytes with a 32-byte line size, and is two-way set associative. each cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to physical addresses. the data cache is configurable to be write back or write through on a line-by-line basis and follows the mesi protocol. the data cache tags are triple-ported to support two data transfers and an inquire cycle in the same clock. the code cache is an inherently write-protected cache. the code cache tags are also triple-ported to support snooping and split-line accesses. individual pages can be configured as cacheable or non-cacheable by software or hardware. the caches can be enabled or disabled by software or hardware. pentium processors have a 64-bit data bus for fast data transfer. burst read and burst write back cycles are supported. in addition, bus cycle pipelining allows two bus cycles to occur simultaneously. the memory management unit contains optional extensions to the architecture which allow 2-mbyte and 4-mbyte page sizes. pentium processors have added significant data integrity and error detection capability. data parity checking is still supported on a byte-by-byte basis. address parity checking and internal parity checking features have been added along with a new exception, the machine check exception. pentium processors offer functional redundancy checking to provide maximum error detection of the processor and the interface to the processor. when functional redundancy checking is used, a second processor, the checker executes in lock-step with the master processor. the checker samples the masters outputs, compares those values with the values it computes internally, and asserts an error signal when a mismatch occurs. as more and more functions are integrated on-chip, the complexity of board level testing is increased. to address this, pentium processors provide test and debug capability. pentium processors implement ieee boundary scan (standard 1149.1). in addition, pentium processors provide four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken.
embedded pentium ? processor datasheet 9 system management mode (smm) has been implemented along with some extensions to the smm architecture. enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. figure 1 is a block diagram of the embedded pentium processor. the block diagram shows the two instruction pipelines, the u pipe and the v pipe. the u-pipe can execute all integer and floating-point instructions. the v-pipe can execute simple integer instructions and the fxch floating-point instructions. the separate code and data caches are shown in the block diagram. the data cache has two ports, one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). the data cache has a dedicated translation lookaside buffer (tlb) to translate linear addresses to the physical addresses used by the data cache. the code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units. instructions are fetched from the code cache or from the external bus. branch addresses are remembered by the branch target buffer. the code cache tlb translates linear addresses to physical addresses used by the code cache. figure 1. embedded pentium ? processor block diagram a6053-01 dp logic control rom control unit address generate (u pipeline) address generate (v pipeline) control bus unit 64-bit data bus 32-bit address bus control apic tlb data cache 8 kbytes data control branch target buffer prefetch address instruction pointer prefetch buffers instruction decode code cache 8 kbytes tlb 256 64 32 32 32 32 32 32 80 80 control add floating point unit register file 64-bit data bus 32-bit addr. bus 32 integer register file alu (u pipline) alu (v pipline) barrel shifter branch verification and target address divide multiply page unit
embedded pentium ? processor 10 datasheet the decode unit decodes the prefetched instructions so the processor can execute the instruction. the control rom contains microcode to control the sequence of operations that must be performed to implement the pentium processor architecture. the control rom unit has direct control over both pipelines. pentium processors contain a pipelined floating-point unit that provides a significant floating-point performance advantage over previous generations of processors. symmetric dual processing in a system is supported with two pentium processors. the two processors appear to the system as a single processor. operating systems with dual processing support properly schedule computing tasks between the two processors. this scheduling of tasks is transparent to software applications and the end-user. logic built into the processors supports a glueless interface for easy system design. through a private bus, the two pentium processors arbitrate for the external bus and maintain cache coherency. dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. in this document, in order to distinguish between two pentium processors in dual processing mode, one processor is the primary processor and the other is the dual processor. note that this is a different concept than that of master and checker processors described in the discussion on functional redundancy on page 8. the pentium processor supports clock control. when the clock to the processor is stopped, power dissipation is virtually eliminated. this makes the pentium processor a good choice for energy- efficient designs. the pentium processor supports fractional bus operation. this allows the processor core to operate at high frequencies, while communicating with the external bus at lower frequencies. the pentium processor contains an on-chip advanced programmable interrupt controller (apic). this apic implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple i/o subsystem support, 8259a compatibility, and inter-processor interrupt support. pentium processor architectural features are described in more detail in the embedded pentium ? processor family developers manual (order number 273204). 1.2 pentium ? processors with voltage reduction technology the embedded pentium processor with voltage reduction technology is described in the embedded pentium ? processor with voltage reduction technology datasheet (order number 273203).
embedded pentium ? processor datasheet 11 2.0 packaging information 2.1 pentium ? processor pinout figure 2. pentium ? processor spga package pinout (top side view) a5498-01 37 35 33 36 34 32 30 28 31 29 272625242322212019181716151413121110987654321 37 35 be6# nc nc v cc v cc cputyp r v ss v cc t s v ss v cc v cc nc nc v cc v ss stpclk# v u w frcmc# bf0 v cc v ss bf1 x v ss pen# z y ignne# init v cc na# brdyc# v cc wb/wt# phit# v cc brdy# v ss boff# v ss prdy phitm# v cc r/s# nmi v cc hold v ss v ss smi# ab aa ac ad ae apchk# pbreq# v cc d/p# a23 v cc pbgnt# v ss v ss intr pcd smiact# v cc a24 a27 v cc pchk# v ss v ss a21 af ag ah aj ads# hlda breq a25 a31 v ss lock# v ss a22 a26 be2# hitm# be0# buschk# be4# pwt inc a11 nc scyc a3 a7 v ss a12 a14 a16 a18 a20 be7# be3# hit# be1# a20m# be5# d/c# ap a5 reset clk a28 a29 a9 a13 a15 a17 a19 v cc 33 al ak al am an an view of component as mounted on board (pins down) v cc inc v cc flush# v cc inc inc 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10987654321 a10 v cc v cc nc a6 v ss v cc v cc v cc v cc v cc v ss am v ss w/r# v ss v ss v ss eads# adsc# a8 v ss v ss a30 a4 v ss v ss v ss v ss v ss d d4 d5 f e d1 d3 v cc d2 picd0 v ss picclk h g j picd1 v cc v cc v ss d0 k v ss tck m l tdi tdo v cc v ss tms p n q d6 d7 v cc trst# v ss nc dp0 d8 r t s v u w x z y ab aa ac ad ae af ag ah aj ak d f e h g j k m l p n q c b a dp7 d63 v cc ferr# pm0bp0 v cc d62 v ss ierr# v ss bp3 bp2 v cc pm1bp1 v ss inv cache# v cc mi/o# v ss ken# ewbe# v cc ahold v ss d49 d52 d54 d53 d55 v cc d48 d50 d51 dp6 d58 d57 v cc d56 v ss d60 d61 v cc d59 v ss dp5 d42 d46 d30 d33 d40 d44 dp3 dp1 d26 d28 d12 d19 d23 d37 d39 d35 c b a d10 d14 d47 inc d29 d32 dp4 d45 d31 d21 d25 d27 d17 d24 dp2 d36 d38 d34 d9 d11 d13 d43 inc v ss v ss v ss v ss v ss d20 v ss v ss d16 v ss v ss v ss v ss v ss d15 d18 d41 inc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc d22 nc
embedded pentium ? processor 12 datasheet figure 3. pentium ? processor spga package pinout (pin side view) a5499-01 37 35 33 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 37 35 be6# nc nc v cc v cc cputyp r v ss v cc t s v ss v cc v cc nc nc v cc v ss stpclk# v u w frcmc# bf0 v cc v ss bf1 x v ss pen# z y ignne# init v cc na# brdyc# v cc wb/wt# phit# v cc brdy# v ss boff# v ss prdy phitm# v cc r/s# nmi v cc hold v ss v ss smi# ab aa ac ad ae apchk# pbreq# v cc d/p# a23 v cc pbgnt# v ss v ss intr pcd smiact# v cc a24 a27 v cc pchk# v ss v ss a21 af ag ah aj ads# hlda breq a25 a31 v ss lock# v ss a22 a26 be2# hitm# be0# buschk# be4# pwt inc a11 nc scyc a3 a7 v ss a12 a14 a16 a18 a20 be7# be3# hit# be1# a20m# be5# d/c# ap a5 reset clk a28 a29 a9 a13 a15 a17 a19 v cc 33 al ak al am an an pin side view v cc inc v cc flush# v cc inc inc 36 34 32 30 28 31 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a10 v cc v cc nc a6 v ss v cc v cc v cc v cc v cc v ss am v ss w/r# v ss v ss v ss eads# adsc# a8 v ss v ss a30 a4 v ss v ss v ss v ss v ss d d4 d5 f e d1 d3 v cc d2 picd0 v cc v ss picclk h g j picd1 v cc v cc v ss d0 k v ss tck m l tdi tdo v cc v ss tms p n q d6 d7 v cc trst# v ss nc dp0 d8 r t s v u w x z y ab aa ac ad ae af ag ah aj ak d f e h g j k m l p n q c b a dp7 d63 v cc ferr# pm0bp0 v cc d62 v ss ierr# v ss bp3 bp2 v cc pm1bp1 v ss inv cache# v cc mi/o# v ss ken# ewbe# v cc ahold v ss d49 d52 d54 d53 d55 v cc d48 d50 d51 dp6 d58 d57 v cc d56 v ss d60 d61 v cc d59 v ss dp5 d42 d46 d30 d33 d40 d44 dp3 dp1 d26 d28 d12 d19 d23 d37 d39 d35 c b a d10 d14 d47 inc d29 d32 dp4 d45 d31 d21 d25 d27 d17 d24 dp2 d36 d38 d34 d9 d11 d13 d43 inc v ss v ss v ss v ss v ss d20 v ss v ss d16 v ss v ss v ss v ss v ss d15 d18 d41 inc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc d22 nc
embedded pentium ? processor datasheet 13 2.1.1 pin cross reference table 1. pin cross-reference by pin name address and data pins pin location pin location pin location pin location pin location address a3 al35 a9 ak30 a15 ak26 a21 af34 a27 ag33 a4 am34 a10 an31 a16 al25 a22 ah36 a28 ak36 a5 ak32 a11 al31 a17 ak24 a23 ae33 a29 ak34 a6 an33 a12 al29 a18 al23 a24 ag35 a30 am36 a7 al33 a13 ak28 a19 ak22 a25 aj35 a31 aj33 a8 am32 a14 al27 a20 al21 a26 ah34 data d0 k34 d13 b34 d26 d24 d39 d10 d52 e03 d1 g35 d14 c33 d27 c21 d40 d08 d53 g05 d2 j35 d15 a35 d28 d22 d41 a05 d54 e01 d3 g33 d16 b32 d29 c19 d42 e09 d55 g03 d4 f36 d17 c31 d30 d20 d43 b04 d56 h04 d5 f34 d18 a33 d31 c17 d44 d06 d57 j03 d6 e35 d19 d28 d32 c15 d45 c05 d58 j05 d7 e33 d20 b30 d33 d16 d46 e07 d59 k04 d8 d34 d21 c29 d34 c13 d47 c03 d60 l05 d9 c37 d22 a31 d35 d14 d48 d04 d61 l03 d10 c35 d23 d26 d36 c11 d49 e05 d62 m04 d11 b36 d24 c27 d37 d12 d50 d02 d63 n03 d12 d32 d25 c23 d38 c09 d51 f04
embedded pentium ? processor 14 datasheet table 2. pin cross-reference by pin name control pins pin location pin location pin location pin location a20m# ak08 brdyc# y03 flush# an07 pen# z34 ads# aj05 breq aj01 frcmc# y35 pm0/bp0 q03 adsc# am02 buschk# al07 hit# ak06 pm1/bp1 r04 ahold v04 cache# u03 hitm# al05 prdy ac05 ap ak02 cputyp q35 hlda aj03 pwt al03 apchk# ae05 d/c# ak04 hold ab04 r/s# ac35 be0# al09 d/p# ae35 ierr# p04 reset ak20 be1# ak10 dp0 d36 ignne# aa35 scyc al17 be2# al11 dp1 d30 init aa33 smi# ab34 be3# ak12 dp2 c25 intr/ lint0 ad34 smiact# ag03 be4# al13 dp3 d18 inv u05 tck m34 be5# ak14 dp4 c07 ken# w05 tdi n35 be6# al15 dp5 f06 lock# ah04 tdo n33 be7# ak16 dp6 f02 m/io# t04 tms p34 boff# z04 dp7 n05 na# y05 trst# q33 bp2 s03 eads# am04 nmi/lint1 ac33 w/r# am06 bp3 s05 ewbe# w03 pcd ag05 wb/wt# aa05 brdy# x04 ferr# q05 pchk# af04 apic picclk h34 picd0/ [dpen#] j33 picd1/ [apicen] l35 clock control clk ak18 bf0 y33 bf1 x34 stpclk# v34 dual processor private interface pbgnt# ad04 pbreq# ae03 phit# aa03 phitm# ac03
embedded pentium ? processor datasheet 15 2.1.2 design notes for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc . unused active high inputs should be connected to gnd. no connect (nc) pins must remain unconnected. connection of nc pins may result in component failure or incompatibility with processor steppings. 2.1.3 pin quick reference this section gives a brief functional description of each of the pins. for a detailed description, see the pentium ? processor family developers manual (order number 273204). note: all input pins must meet their ac/dc specifications to guarantee proper functional behavior. the # symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage. when a # symbol is not present after the signal name, the signal is active, or asserted at the high voltage level. square brackets around a signal name indicate that the signal is defined only at reset. the following pins become i/o pins when two pentium processors are operating in a dual processing environment: ? ads#, cache#, hit#, hitm#, hlda#, lock#, m/io#, d/c#, w/r#, scyc table 3. pin cross-reference by pin name power, ground and no connect pins v cc a07 a19 e37 l33 s01 w01 ac01 an09 an21 a09 a21 g01 l37 s37 w37 ac37 an11 an23 a11 a23 g37 n01 t34 y01 ae01 an13 an25 a13 a25 j01 n37 u01 y37 ae37 an15 an27 a15 a27 j37 q01 u33 aa01 ag01 an17 an29 a17 a29 l01 q37 u37 aa37 ag37 an19 v ss b06 b18 h02 p02 u35 z36 af36 am12 am24 b08 b20 h36 p36 v02 ab02 ah02 am14 am26 b10 b22 k02 r02 v36 ab36 aj37 am16 am28 b12 b24 k36 r36 x02 ad02 al37 am18 am30 b14 b26 m02 t02 x36 ad36 am08 am20 an37 b16 b28 m36 t36 z02 af02 am10 am22 nc/inc ? a03 b02 r34 s35 w35 al19 an03 an35 a37 c01 s33 w33 al01 an01 an05 ? these pins should be left unconnected. connection of these pins may result in component failure or incompatibility with processor steppings.
embedded pentium ? processor 16 datasheet table 4. pin quick reference (sheet 1 of 5) symbol type ? name and function a20m# i when the address bit 20 mask pin is asserted, the processor emulates the address wraparound at 1 mbyte that occurs on the 8086 by masking physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a20m# is internally masked by the processor when configured as a dual processor. a31Ca3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31Ca5. ads# o the address strobe indicates that a new valid bus cycle is currently being driven by the processor. adsc# o the additional address strobe signal is functionally identical to ads#. this signal can be used to relieve tight board timings by easing the load on the ads# signal. ahold i in response to the assertion of address hold , the processor stops driving the address lines (a31Ca3), and ap in the next clock. the rest of the bus remains active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the processor with even parity information on all processor generated cycles in the same clock in which the address is driven. even parity must be driven back to the processor during inquire cycles on this pin in the same clock as eads# to ensure that the correct parity check status is indicated by the processor. apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the processor has detected a parity error on the address bus during inquire cycles. apchk# remains active for one clock each time a parity error is detected (including during dual processing private snooping). [apicen] picd1 i advanced programmable interrupt controller enable enables or disables the onC chip apic interrupt controller. if sampled high at the falling edge of reset, the apic is enabled. apicen shares a pin with the picd1 signal. be7#Cbe5# be4#Cbe0# o i/o the byte enable pins determine which bytes must be written to external memory, or which bytes were requested by the cpu for the current cycle. the byte enables are driven in the same clock as the address lines (a31Ca3). the lower four byte enable pins (be3#Cbe0#) are used as apic id inputs and are sampled at reset. in dual processing mode, be4# is used as an input during flush cycles. bf1Cbf0 i bus frequency determines the bus-to-core frequency ratio. bf1Cbf0 are sampled at reset, and cannot be changed until another non-warm (1 ms) assertion of reset. additionally, bf1Cbf0 must not change values while reset is active. see table 5 for bus frequency selections. boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the processor floats all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time the processor restarts the aborted bus cycle(s) in their entirety. bp3Cbp2 pm1/bp1C pm0/bp0 o the breakpoint pins (bp3Cbp0) correspond to the debug registers, dr3Cdr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. ? the pins are classified as input or output based on their function in master mode. see the pentium ? processor family developers manual (order number 273204) for more information.
embedded pentium ? processor datasheet 17 brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. brdyc# i the additional burst ready signal has the same functionality as brdy#. this signal can be used to relieve tight board timings by easing the load on the burst ready signal. breq o the bus request output indicates to the external system that the processor has internally generated a bus request. this signal is always driven whether or not the processor is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. when this pin is sampled active, the processor latches the address and control signals in the machine check registers. when buschk# is asserted and the mce bit in cr4 is set, the processor vectors to the machine check exception. to ensure that buschk# is always recognized, stpclk# must be deasserted any time buschk# is asserted by the system, before the system allows another external bus cycle. when buschk# is asserted by the system for a snoop cycle while stpclk# remains asserted, normally (when mce=1) the processor vectors to the exception after stpclk# is deasserted. when another snoop to the same line occurs during stpclk# assertion, the processor can lose the buschk# request. cache# o for processor-initiated cycles, the cacheability pin indicates internal cacheability of the cycle (if a read), and indicates a burst write back cycle (if a write). when this pin is driven inactive during a read cycle, the processor does not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for the processor. its frequency is the operating frequency of the processors external bus, and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst#, and picd1Cpicd0 are specified with respect to the rising edge of clk. it is recommended that clk begin toggling within 150 ms after v cc reaches its proper operating level. this recommendation is to ensure long-term reliability of the device. cputyp i cpu type distinguishes the primary processor from the dual processor. in a single processor environment, or when the processor is acting as the primary processor in a dual processing system, cputyp should be strapped to v ss . the dual processor should have cputyp strapped to v cc . d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock in which the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. d/p# o the dual/primary processor indication. the primary processor drives this pin low when it is driving the bus, otherwise it drives this pin high. d/p# is always driven. d/p# can be sampled for the current cycle with ads# (like a status pin). this pin is defined only on the primary processor. dual processing is supported in a system only if both processors are operating at identical core and bus frequencies. within these restrictions, two processors of different steppings may operate together in a system. d63Cd0 i/o these are the 64 data lines for the processor. lines d7Cd0 define the least significant byte of the data bus; lines d63Cd56 define the most significant byte of the data bus. when the cpu is driving the data lines, they are driven during the t2, t12, or t2p clocks for that cycle. during reads, the cpu samples the data bus when brdy# is returned. table 4. pin quick reference (sheet 2 of 5) symbol type ? name and function ? the pins are classified as input or output based on their function in master mode. see the pentium ? processor family developers manual (order number 273204) for more information.
embedded pentium ? processor 18 datasheet dp7Cdp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by the pentium processor with even parity information on writes in the same clock as write data. even parity information must be driven back to the processor on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the pentium processor. dp7 applies to d63Cd56, dp0 applies to d7Cd0. [dpen#] picd0 i/o dual processing enable is an output of the dual processor and an input of the primary processor. the dual processor drives dpen# low to the primary processor at reset to indicate that the primary processor should enable dual processor mode. dpen# may be sampled by the system at the falling edge of reset to determine if the dual-processor socket is occupied. dpen# shares a pin with picd0. eads# i the external address strobe signal indicates that a valid external address has been driven onto the processor address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when the processor generates a write, and ewbe# is sampled inactive, the processor holds off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using dos-type floating-point error reporting. ferr# is never driven active by the dual processor. flush# i when asserted, the cache flush input forces the processor to write back all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle is generated by the processor to indicate completion of the write back and invalidation. when flush# is sampled low when reset transitions from high to low, three-state test mode is entered. if two pentium processors are operating in dual processing mode and flush# is asserted, the dual processor performs a flush first (without a flush acknowledge cycle), then the primary processor performs a flush followed by a flush acknowledge cycle. when the flush# signal is asserted in dual processing mode, it must be deasserted at least one clock prior to brdy# of the flush acknowledge cycle to avoid dp arbitration problems. frcmc# i the functional redundancy checking master/checker mode input is used to determine whether the processor is configured in master mode or checker mode. when configured as a master, the processor drives its output pins as required by the bus protocol. when configured as a checker, the processor three-states all outputs (except ierr# and tdo) and samples the output pins. the configuration as a master/checker is set after reset and may not be changed other than by a subsequent reset. hit# o the inquire cycle hit/miss indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either the processor data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the processor cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the inquire cycle hit/miss to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after an inquire cycle that results in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. table 4. pin quick reference (sheet 3 of 5) symbol type ? name and function ? the pins are classified as input or output based on their function in master mode. see the pentium ? processor family developers manual (order number 273204) for more information.
embedded pentium ? processor datasheet 19 hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that the processor has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda is driven inactive and the processor resumes driving the bus. when the processor has a bus cycle pending, it is driven in the same clock in which hlda is deasserted. hold i in response to the bus hold request , the processor floats most of its output and input/output pins and asserts hlda after completing all outstanding bus cycles. the processor maintains its bus in this state until hold is deasserted. hold is not recognized during lock cycles. the processor recognizes hold during reset. ierr# o the internal error pin is used to indicate two types of errors, internal parity errors and functional redundancy errors. when a parity error occurs on a read from an internal array, the processor asserts the ierr# pin for one clock and then shuts down. when the processor is configured as a checker and a mismatch occurs between the value sampled on the pins and the corresponding value computed internally, the processor asserts ierr# two clocks after the mismatched value is returned. lock# o the bus lock pin indicates that the current bus cycle is locked. the processor does not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be deasserted for at least one clock between back-to-back locked cycles. m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock in which the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the processor issues ads# for a pending cycle two clocks after na# is asserted. the processor supports up to two outstanding bus cycles. nmi/lint1 i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. when the local apic is enabled, this pin becomes lint1. pbgnt# i/o when two pentium processors are configured in dual processing mode, private bus grant is the grant line that is used to perform private bus arbitration. pbgnt# should be left unconnected if only one pentium processor exists in a system. pbreq# i/o when two pentium processors are configured in dual processing mode, private bus request is the request line that is used to perform private bus arbitration. pbreq# should be left unconnected if only one pentium processor exists in a system. pcd o the page cacheability disable pin reflects the state of the pcd bit in cr3, the page directory entry, or the page table entry. the purpose of pcd is to provide an external cacheability indication on a page-by-page basis. pchk# o the data parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. when two pentium processors are operating in dual processing mode, pchk# may be driven two or three clocks after brdy# is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception is taken as a result of a data parity error on a read cycle. when this pin is sampled active in the clock during which a data parity error is detected, the processor latches the address and control signals of the cycle with the parity error in the machine check registers. when pen# is active and the machine check enable bit in cr4 is set to 1, the processor vectors to the machine check exception before the beginning of the next instruction. table 4. pin quick reference (sheet 4 of 5) symbol type ? name and function ? the pins are classified as input or output based on their function in master mode. see the pentium ? processor family developers manual (order number 273204) for more information.
embedded pentium ? processor 20 datasheet phit# i/o private inquire cycle hit/miss is a hit indication used to maintain local cache coherency when two pentium processors are configured in dual processing mode. phit# should be left unconnected if only one pentium processor exists in a system. phitm# i/o private inquire cycle hit/miss to a modified line is a hit indication used to maintain local cache coherency when two pentium processors are configured in dual processing mode. phitm# should be left unconnected if only one pentium processor exists in a system. picclk i the apic interrupt controller serial data bus clock is driven into the processor interrupt controller clock input of the processor. picd1/[dpen#]C picd0/[apicen] i/o processor interrupt controller data lines 0 C 1 of the processor comprise the data portion of the apic 3-wire bus. they are open-drain outputs that require external pull-up resistors. these signals share pins with dpen# and apicen respectively. pm1/bp1C pm0/bp0 o these pins function as part of the performance monitoring feature. the breakpoint 1C0 pins are multiplexed with the performance monitoring 1 C 0 pins. the pb1 and pb0 bits in the debug mode control register determine whether the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active, or probe mode being entered. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode. stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the processor, which causes the core to consume less power. when the processor recognizes stpclk#, the processor stops execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generates a stop grant acknowledge cycle. when stpclk# is asserted, the processor still responds to interprocessor and external snoop requests. tck i the testability clock input provides the clocking function for the pentium processor boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the processor during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the processor on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of the processor on the tdo pin on tcks falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. v cc i the pentium processor has 53 3.3 v power inputs. v ss i the pentium processor has 53 ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock in which the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the write back/write through input allows a data cache line to be defined as write back or write through on a line-by-line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. table 4. pin quick reference (sheet 5 of 5) symbol type ? name and function ? the pins are classified as input or output based on their function in master mode. see the pentium ? processor family developers manual (order number 273204) for more information.
embedded pentium ? processor datasheet 21 2.1.4 pin reference tables table 5. bus frequency selections pentium ? processor core frequency (max) external bus frequency (max) bus/core ratio bf1 bf0 166 mhz 66 mhz 2/5 0 0 133 mhz 66 mhz 1/2 1 0 100 mhz 66 mhz 2/3 1 1 table 6. output pins name active level 1 when floated ads# 2 low bus hold, boff# adsc# low bus hold, boff# apchk# low be7#Cbe5# low bus hold, boff# breq high cache# 2 low bus hold, boff# d/p# 3 n/a ferr# 3 low hit# 2 low hitm# 2 low hlda 2 high ierr# low lock# 2 low bus hold, boff# m/io# 2 , d/c# 2 , w/r# 2 n/a bus hold, boff# pchk# low bp3Cbp2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc 2 high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir notes: 1. all output and input/output pins are floated during three-state test mode and checker mode (except ierr#). 2. these are i/o signals when two pentium processors are operating in dual processing mode. 3. these signals are undefined when the processor is configured as a dual processor.
embedded pentium ? processor 22 datasheet table 7. input pins name active level synchronous/ asynchronous internal resistor qualified a20m# ? low asynchronous ahold high synchronous bf1Cbf0 high synchronous/reset pullup boff# low synchronous brdy# low synchronous bus state t2, t12, t2p brdyc# low synchronous pullup bus state t2, t12, t2p buschk# low synchronous pullup brdy# clk n/a cputyp high synchronous/reset eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous frcmc# low asynchronous hold high synchronous ignne# ? low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous pen# low synchronous brdy# picclk high asynchronous pullup r/s# n/a asynchronous pullup reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup wb/wt# n/a synchronous first brdy#/na# ? undefined when the processor is configured as a dual processor.
embedded pentium ? processor datasheet 23 table 8. input/output pins name active level when floated 1 qualified (when an input) internal resistor a31Ca3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be4#Cbe0# low address hold, bus hold, boff# reset pulldown 2 d63Cd0 n/a bus hold, boff# brdy# dp7Cdp0 n/a bus hold, boff# brdy# picd0[dpen#] pullup picd1[apicen] pulldown notes: 1. all output and input/output pins are floated during three-state test mode (except tdo) and checker mode (except ierr# and tdo). 2. be3#Cbe0# have pulldowns during reset only. table 9. inter-processor input/output pins name ? active level internal resistor phit# low pullup phitm# low pullup pbgnt# low pullup pbreq# low pullup ? for proper interprocessor operation, the system cannot load these signals.
embedded pentium ? processor 24 datasheet 2.1.5 pin grouping according to function table 10. pin functional grouping function pins clock clk initialization reset, init, bf1Cbf0 address bus a31Ca3, be7#Cbe0# address mask a20m# data bus d63Cd0 address parity ap, apchk# apic support picclk, picd1Cpicd0 data parity dp7Cdp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, adsc#, brdy#, brdyc#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda dual processing private bus control pbgnt#, pbreq#, phit#, phitm# interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# functional redundancy checking frcmc# (ierr#) tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3Cbp2 power management stpclk# miscellaneous dual processing cputyp, d/p# probe mode r/s#, prdy
embedded pentium ? processor datasheet 25 2.2 mechanical specifications the embedded pentium processor is packaged in a 296-pin ceramic staggered pin grid array (spga) package. the pins are arranged in a 37 x 37 matrix and the package dimensions are 1.95" x 1.95" (table 11). figure 4 and table 12 show the package dimensions. table 11. package information summary for pentium ? processor package type total pins pin array package size ceramic staggered pin grid array spga 296 37 x 37 1.95" x 1.95" 4.95 cm x 4.95 cm figure 4. spga package dimensions table 12. spga package dimensions key symbol millimeters inches min max notes min max notes a 2.62 2.97 0.103 0.117 a 1 0.69 0.84 metal lid 0.027 0.033 metal lid a 2 3.31 3.81 metal lid 0.130 0.150 metal lid b 0.43 0.51 0.017 0.020 d 49.28 49.78 1.940 1.960 d 1 45.59 45.85 1.795 1.805 e 1 2.29 2.79 0.090 0.110 l 3.05 3.30 0.120 0.130 n 296 lead count 296 lead count s 1 1.52 2.54 0.060 0.100 d d d 1 a 1 a 2 0b e 1 s 1 2.29 1.52 45 ? chamfer (index corner) ref. 01.65 ref. l seating plane pin c3 a s 1 d 1
embedded pentium ? processor 26 datasheet 2.3 thermal specifications the pentium processor is specified for proper operation when case temperature, t case (t c ), is within the specified range of 0 c to 70 c. the power dissipation specification in table 13 is provided for designing thermal solutions for operation at a sustained maximum level. this is the worst-case power the device would dissipate in a system. this number is used for design of a thermal solution for the device. 2.3.1 measuring thermal values to verify that the proper t c (case temperature) is maintained, it should be measured at the center of the package top surface (opposite of the pins). the measurement is made in the same way with or without a heatsink attached. when a heatsink is attached, a hole (0.150" diameter or smaller) should be drilled through the heatsink to allow a probe to touch the center of the package. see figure 5 for an illustration of how to measure t c . to minimize the measurement errors, use the following approach: ? use 36-gauge or finer diameter k, t, or j type thermocouples. ? attach the thermocouple bead or junction to the center of the package top surface using high thermal conductivity cements. ? attach the thermocouple at a 90-degree angle as shown in figure 5. ? the hole size should be 0.150" or less in diameter. table 13. power dissipation requirements for thermal solution design parameter typical 1 max unit notes active power dissipation 5.4 4.3 3.9 14.5 2 11.2 3 10.1 3 watts 166 mhz 133 mhz 100 mhz stop grant and auto halt powerdown power dissipation 2.1 1.7 1.55 watts 166 mhz, note 4 133 mhz, note 4 100 mhz, note 4 stop clock power dissipation 0.02 <0.3 watts note 5 notes: 1. this is the typical power dissipation in a system. this value was the average value measured in a system using a typical device at nominal v cc (3.3 v for 100 and 133 mhz processors and 3.5 v for 166 mhz processors) running typical applications. this value is highly dependent upon the specific system configuration. 2. systems must be designed to thermally dissipate the maximum active power of the device. it is determined using a worst-case instruction mix with v cc =3.5 v, and also takes into account the thermal time constants of the package. 3. systems must be designed to thermally dissipate the maximum active power of the device. it is determined using a worst case instruction mix with v cc = 3.3 v and also takes into account the thermal time constants of the package. 4. stop grant/auto halt powerdown power dissipation is determined by asserting the stpclk# pin or executing the halt instruction. 5. stop clock power dissipation is determined by asserting the stpclk# pin and then removing the external clk input.
embedded pentium ? processor datasheet 27 2.3.2 thermal equations and data for the pentium processor, an ambient temperature, t a (air temperature around the processor), is not specified directly. the only restriction is that the case temperature (t c ) is met. to calculate t a values, use the following equations: t a = t c C (p * q ca ) q ca = q ja C q jc where: t a and t c = ambient and case temperature ( c) q ca = case-to-ambient thermal resistance ( c/w) q ja = junction-to-ambient thermal resistance ( c/w) q jc = junction-to-case thermal resistance ( c/w) p = maximum power consumption in watts (see table 13) table 14 lists the q ca values for the pentium processor with passive heatsinks. thermal data collection parameters: ? heatsinks are omnidirectional pin aluminum alloy ? features were based on standard extrusion practices for a given height ? pin size ranged from 50 to 129 mils ? pin spacing ranged from 93 to 175 mils ? base thickness ranged from 79 to 200 mils ? heatsink attach was 0.005" of thermal grease ? using an attach thickness of 0.002 improves performance by approximately 0.3 c/w figure 5. technique for measuring case temperature (t c )
embedded pentium ? processor 28 datasheet table 14. thermal resistances for embedded pentium ? processors heatsink height in inches q jc (c/watt) q ca (c/watt) vs. laminar airflow (linear ft/min) 0 100 200 400 600 800 0.25 1.25 9.4 8.3 6.9 4.7 3.9 3.3 0.35 1.25 9.1 7.8 6.3 4.3 3.6 3.1 0.45 1.25 8.7 7.3 5.6 3.9 3.2 2.8 0.55 1.25 8.4 6.8 5.0 3.5 2.9 2.6 0.65 1.25 8.0 6.3 4.6 3.3 2.7 2.4 0.80 1.25 7.3 5.6 4.2 2.9 2.5 2.3 1.00 1.25 6.6 4.9 3.9 2.9 2.4 2.1 1.20 1.25 6.2 4.6 3.6 2.7 2.3 2.1 1.40 1.25 5.7 4.2 3.3 2.5 2.2 2.0 without heatsink 1.7 14.5 13.8 12.6 10.5 8.6 7.5
embedded pentium ? processor datasheet 29 3.0 electrical specifications this section describes the dc and ac specifications for the embedded pentium processor. 3.1 3.3 v power supply the processor has all v cc 3.3-v inputs. the clk and picclk inputs can tolerate a 5-v input signal. this allows the processor to use 5-v or 3.3-v clock drivers. 3.2 3.3 v inputs and outputs the inputs and outputs of the processor are 3.3 v jedec standard levels. both inputs and outputs are also ttl-compatible, although the inputs cannot tolerate voltage swings above the 3.3 v v in max. the clk and picclk inputs of the processor are 5 v tolerant. this allows a 5-v clock driver to drive the processor. all other pins are 3.3 v only. for processor outputs, if the system support components use ttl-compatible inputs, the components will interface to the processor without extra logic. this is because the processor drives according to the 5-v ttl specification (but not beyond 3.3 v). for processor inputs, the voltage must not exceed the 3.3 v v ih3 maximum specification. system support components can consist of 3.3 v devices or open-collector devices. in an open-collector configuration, the external resistor can be biased with the processors v cc . as the processors v cc changes from 5 v to 3.3 v, so does this signals maximum drive. 3.3 absolute maximum ratings functional operating conditions are given in the ac and dc specification tables. functional operation at the maximums is not implied or guaranteed. extended operation beyond the maximum ratings may affect device reliability. furthermore, although the pentium processor contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only.
embedded pentium ? processor 30 datasheet 3.4 dc specifications tables 16 C18 list the dc specifications that apply to the pentium processor. the pentium processor is a 3.3 v part internally. the clk and picclk inputs may be 3.3 v or 5 v inputs. since the 3.3 v (5 v-safe) input levels defined in table 16 are the same as the 5 v ttl levels, the clk and picclk inputs are compatible with existing 5 v clock drivers. table 15. absolute maximum ratings parameter maximum rating case temperature under bias - 65 c to 110 c storage temperature - 65 c to 150 c 3 v supply voltage with respect to v ss - 0.5 v to +4.6 v 3 v only buffer dc input voltage - 0.5 v to v cc + 0.5; not to exceed v cc3 max 1 5 v safe buffer dc input voltage - 0.5 v to 6.5 v 2,3 notes: 1. applies to all pentium ? processor inputs except clk and picclk. 2. applies to clk and picclk. 3. see overshoot/undershoot transient specification. table 16. 3.3 v dc specifications t case = 0 to 70 c; 3.135 v < v cc < 3.6 v for 100 and 133 mhz devices t case = 0 to 70 c; 3.4 v < v cc < 3.6 v for 166 mhz (vre device) symbol parameter min max unit notes v il3 input low voltage C0.3 0.8 v ttl level, note 1 v ih3 input high voltage 2.0 v cc +0.3 v ttl level, note 1 v ol3 output low voltage 0.4 v ttl level, note 2, note 1 v oh3 output high voltage 2.4 v ttl level, note 3, note 1 i cc3 power supply current 4250 3400 3250 ma ma ma 166 mhz, note 4 133 mhz, note 4 100 mhz, note 4 notes: 1. 3.3 v ttl levels apply to all signals except clk and picclk. 2. parameter measured at 4 ma. 3. parameter measured at 3 ma. 4. this value should be used for power supply design. it was determined using a worst-case instruction mix and v cc = 3.6 v. power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. for more information, refer to decoupling recommendations on page 32. table 17. 3.3 v (5 v-safe) dc specifications symbol parameter min max unit notes v il5 input low voltage C0.3 0.8 v ttl level ? v ih5 input high voltage 2.0 5.55 v ttl level ? ? applies to clk and picclk only.
embedded pentium ? processor datasheet 31 3.5 ac specifications the ac specifications of the pentium processor consist of setup times, hold times, and valid delays at 0 pf. 3.5.1 private bus when two pentium processor are operating in dual processor mode, a private bus exists to arbitrate for the processor bus and maintain local cache coherency. the private bus consists of two pinout changes: 1. five pins are added: pbreq#, pbgnt#, phit#, phitm#, d/p#. 2. ten output pins become i/o pins: ads#, d/c#, w/r#, m/io#, cache#, lock#, hit#, hitm#, hlda, scyc. the new pins are given ac specifications of valid delays at 0 pf, setup times, and hold times. simulate with these parameters and their respective i/o buffer models to guarantee that proper timings are met. the ac specification gives input setup and hold times for the ten signals that become i/o pins. these setup and hold times must only be met when a dual processor is present in the system. 3.5.2 power and ground for clean on-chip power distribution, the pentium processor has 53 v cc (power) and 53 v ss (ground) inputs. power and ground connections must be made to all external v cc and v ss pins of the processor. on the circuit board all v cc pins must be connected to a v cc plane. all v ss pins must be connected to a v ss plane. table 18. input and output characteristics symbol parameter min max unit notes c in input capacitance 15 pf guaranteed by design. c o output capacitance 20 pf guaranteed by design. c i/o i/o capacitance 25 pf guaranteed by design. c clk clk input capacitance 15 pf guaranteed by design. c tin test input capacitance 15 pf guaranteed by design. c tout test output capacitance 20 pf guaranteed by design. c tck test clock capacitance 15 pf guaranteed by design. i li input leakage current 0 < v in < v cc3 , this parameter is for input without pullup or pulldown. i lo output leakage current 0 < v in < v cc3 , this parameter is for input without pullup or pulldown. i ih input leakage current 200 v in = 2.4 v, this parameter is for input with pulldown. i il input leakage current C400 v in = 0.4 v, this parameter is for input with pullup.
embedded pentium ? processor 32 datasheet 3.5.3 decoupling recommendations liberal decoupling capacitance should be placed near the processor. transient power surges can occur when the processor is driving its address and data buses at high frequencies. this is most common when driving large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical performance. inductance can be reduced by minimizing the length of the circuit board traces between the processor and the decoupling capacitors. these capacitors should be evenly distributed around each component on the 3.3 v plane. capacitor values should be chosen to ensure that they eliminate both low and high frequency noise components. for the pentium processor, the power consumption can transition from a low power level to a much higher level (or high-to-low power) very rapidly. a typical example is when entering or exiting the stop grant state. other examples are when executing a halt instruction (causing the processor to enter the auto halt powerdown state) or when transitioning from halt to the normal state. all these examples may cause abrupt changes in the power being consumed by the processor. note that the auto halt powerdown feature is always enabled even when other power management features are not implemented. bulk storage capacitors with a low esr (effective series resistance) in the 10 to 100 f range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point at which the regulated power supply output reacts to the change in load. in order to reduce the esr, it may be necessary to place several bulk storage capacitors in parallel. these capacitors should be placed near the processor (on the 3.3 v plane) to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. 3.5.4 connection specifications all nc and inc pins must remain unconnected. for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc . unused active high inputs should be connected to ground. 3.5.5 ac timing tables the ac specifications given in table 19 and table 20 consist of output delays, input setup requirements and input hold requirements for a 66-mhz external bus. all ac specifications (with the exception of those for the tap signals and apic signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 v for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct processor operation. each valid delay is specified for a 0 pf load. the system designer should use i/o buffer models to account for signal flight time delays. the following applies to all standard ttl signals used with the pentium processor family: ? ttl input test waveforms are assumed to be 0 to 3 v transitions with 1 v/ns rise and fall times. ? 0.3 v/ns input rise/fall time 5 v/ns.
embedded pentium ? processor datasheet 33 table 19. ac specifications (sheet 1 of 3) t case = 0 to 70 c; 3.135 v < v cc < 3.6 v for 100 and 133 mhz devices, c l = 0 pf t case = 0 to 70 c; 3.4 v < v cc < 3.6 v for 166 mhz (vre device), c l = 0 pf symbol parameter min max unit figure notes frequency 33.33 66.6 mhz t 1a clk period 15.0 30.0 ns 6 t 1b clk period stability ps adjacent clocks, notes 1, 21 t 2 clk high time 4.0 ns 6 2 v, note 1 t 3 clk low time 4.0 ns 6 0.8 v, note 1 t 4 clk fall time 0.15 1.5 ns 7 2.0 vC0.8 v, note 1 t 5 clk rise time 0.15 1.5 ns 6 0.8 vC2.0 v, note 1 t 6a pwt, pcd, cache# valid delay 1.0 7.0 ns 7 t 6b ap valid delay 1.0 8.5 ns 7 t 6c be7#Cbe0#, lock# valid delay 0.9 7.0 ns 7 t 6d ads# valid delay 0.8 6.0 ns 7 t 6e adsc#, d/c#, w/r#, scyc, valid delay 0.8 7.0 ns 7 t 6f m/io# valid delay 0.8 5.9 ns 7 t 6g a16Ca3 valid delay 0.5 6.3 ns 7 t 6h a31Ca17 valid delay 0.6 6.3 ns 7 t 7 ads#, adsc#, ap, a31Ca3, pwt, pcd, be7#Cbe0#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 8 1 t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 7 3 t 8b pchk# valid delay 1.0 7.0 ns 7 3 t 9a breq valid delay 1.0 8.0 ns 7 3 t 9b smiact# valid delay 1.0 7.3 ns 7 3 t 9c hlda valid delay 1.0 6.8 ns 7 t 10a hit# valid delay 1.0 6.8 ns 7 t 10b hitm# valid delay 0.7 6.0 ns 7 t 11a pm1Cpm0, bp3Cbp0 valid delay 1.0 10.0 ns 7 t 11b prdy valid delay 1.0 8.0 ns 7 t 12 d63Cd0, dp7Cdp0 write data valid delay 1.3 7.5 ns 7 t 13 d63Cd0, dp3Cdp0 write data float delay 10.0 ns 8 1 t 14 a31Ca5 setup time 6.0 ns 9 22 t 15 a31Ca5 hold time 1.0 ns 9 t 16a inv, ap setup time 5.0 ns 9 t 16b eads# setup time 5.0 ns 9 t 17 eads#, inv, ap hold time 1.0 ns 9 t 18a ken# setup time 5.0 ns 9 t 18b na#, wb/wt# setup time 4.5 ns 9 note: see table 21 for notes.
embedded pentium ? processor 34 datasheet t 19 ken#, wb/wt#, na# hold time 1.0 ns 9 t 20 brdy#, brdyc# setup time 5.0 ns 9 t 21 brdy#, brdyc# hold time 1.0 ns 9 t 22 ahold, boff# setup time 5.5 ns 9 t 23 ahold, boff# hold time 1.0 ns 9 t 24a buschk#, ewbe#, hold setup time 5.0 ns 9 t 24b pen# setup time 4.8 ns 9 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 9 t 25b hold hold time 1.5 ns 9 t 26 a20m#, intr, stpclk# setup time 5.0 ns 9 9, 12 t 27 a20m#, intr, stpclk# hold time 1.0 ns 9 10 t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 9 9, 12, 13 t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 9 10 t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks 11, 13 t 31 r/s# setup time 5.0 ns 9 9, 12, 13 t 32 r/s# hold time 1.0 ns 9 10 t 33 r/s# pulse width, async. 2.0 clks 11, 13 t 34 d63Cd0, dp7Cdp0 read data setup time 2.8 ns 9 t 35 d63Cd0, dp7Cdp0 read data hold time 1.5 ns 9 t 36 reset setup time 5.0 ns 10 8, 9, 12 t 37 reset hold time 1.0 ns 10 8, 10 t 38 reset pulse width, v cc & clk stable 15.0 clks 10 8, 13 t 39 reset active after v cc & clk stable 1.0 ms 10 power up t 40 reset configuration signals (init, flush#, frcmc#) setup time 5.0 ns 10 9, 12, 13 t 41 reset configuration signals (init, flush#, frcmc#) hold time 1.0 ns 10 10 t 42a reset configuration signals (init, flush#, frcmc#) setup time, async. 2.0 clks 10 to reset falling edge, note 12 t 42b reset configuration signals (init, flush#, frcmc#, brdyc#, buschk#) hold time, async. 2.0 clks 10 to reset falling edge, note 23 t 42d reset configuration signal brdyc# hold time, reset driven synchronously 1.0 ns to reset falling edge, 1, 23 t 43a bf, cputyp setup time 1.0 ms 10 to reset falling edge, note 18 t 43b bf, cputyp hold time 2.0 clks 10 to reset falling edge, note 18 table 19. ac specifications (sheet 2 of 3) t case = 0 to 70 c; 3.135 v < v cc < 3.6 v for 100 and 133 mhz devices, c l = 0 pf t case = 0 to 70 c; 3.4 v < v cc < 3.6 v for 166 mhz (vre device), c l = 0 pf symbol parameter min max unit figure notes note: see table 21 for notes.
embedded pentium ? processor datasheet 35 t 43c apicen, be4# setup time 2.0 clks 10 to reset falling edge t 43d apicen, be4# hold time 2.0 clks 10 to reset falling edge t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 6 t 46 tck high time 25.0 ns 6 2 v, note 1 t 47 tck low time 25.0 ns 6 0.8 v, note 1 t 48 tck fall time 5.0 ns 6 2.0 vC0.8 v, notes 1,5,6 t 49 tck rise time 5.0 ns 6 0.8 vC2.0 v, notes 1,5,6 t 50 trst# pulse width 40.0 ns 12 asynchronous, note 1 t 51 tdi, tms setup time 5.0 ns 11 4 t 52 tdi, tms hold time 13.0 ns 11 4 t 53 tdo valid delay 3.0 20.0 ns 11 5 t 54 tdo float delay 25.0 ns 11 1, 5 t 55 all non-test outputs valid delay 3.0 20.0 ns 11 2, 5, 7 t 56 all non-test outputs float delay 25.0 ns 11 1, 2, 5, 7 t 57 all non-test inputs setup time 5.0 ns 11 2, 4, 7 t 58 all non-test inputs hold time 13.0 ns 11 2, 4, 7 apic ac specifications t 60a picclk frequency 2.0 16.66 mhz t 60b picclk period 60.0 500.0 ns 6 t 60c picclk high time 15.0 ns 6 t 60d picclk low time 15.0 ns 6 t 60e picclk rise time 0.15 2.5 ns 6 t 60f picclk fall time 0.15 2.5 ns 6 t 60g picd1Cpicd0 setup time 3.0 ns 9 to picclk t 60h picd1Cpicd0 hold time 2.5 ns 9 to picclk t 60i picd1Cpicd0 valid delay (ltoh) 4.0 38.0 ns 7 from picclk, notes 24, 25 t 60j picd1Cpicd0 valid delay (htol) 4.0 22.0 ns 7 from picclk, notes 24, 25 t 61 picclk setup time 5.0 ns to clk, note 26 t 62 picclk hold time 2.0 ns to clk, note 26 t 63 picclk ratio (clk/picclk) 4 27 table 19. ac specifications (sheet 3 of 3) t case = 0 to 70 c; 3.135 v < v cc < 3.6 v for 100 and 133 mhz devices, c l = 0 pf t case = 0 to 70 c; 3.4 v < v cc < 3.6 v for 166 mhz (vre device), c l = 0 pf symbol parameter min max unit figure notes note: see table 21 for notes.
embedded pentium ? processor 36 datasheet table 20. dual processor mode ac specifications t case = 0 to 70 c; 3.135 v < v cc < 3.6 v for 100 and 133 mhz devices, c l = 0 pf t case = 0 to 70 c; 3.4 v < v cc < 3.6 v for 166 mhz (vre device), c l = 0 pf symbol parameter min max unit figure notes t 80a pbreq#, pbgnt#, phit# flight time 0 2.0 ns 20, 25 t 80b phitm# flight time 0 1.8 ns 20, 25 t 83a a31Ca5 setup time 3.7 ns 9 14, 17, 22 t 83b d/c#, w/r#, cache#, lock#, scyc setup time t 83c ads#, m/io# setup time 5.8 ns 9 14, 17 t 83d hit#, hitm# setup time 6.0 ns 9 14, 17 t 83e hlda setup time 6.0 ns 9 14, 17 t 84 ads#, d/c#, w/r#, m/io#, cache#, lock#, a31Ca5, hlda, hit#, hitm#, scyc hold time 1.0 ns 9 14, 17 t 85 dpen# valid time 10.0 clks 14, 15, 19 t 86 dpen# hold time 2.0 clks 14, 16, 19 t 87 apic id (be3#Cbe0#) setup time 2.0 clks 10 to reset falling edge, note 19 t 88 apic id (be3#Cbe0#) hold time 2.0 clks 10 from reset falling edge, note 19 t 89 d/p# valid delay 1.0 8.0 ns 7 primary processor only note: see table 21 for table notes.
embedded pentium ? processor datasheet 37 table 21. notes for tables 19 and 20 1. not 100% tested. guaranteed by design/characterization. 2. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 3. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch-free outputs. glitch-free signals monotonically transition without false transitions. 4. referenced to tck rising edge. 5. referenced to tck falling edge. 6. 1 ns can be added to the maximum tck rise and fall times for every 10 mhz of frequency below 33 mhz. 7. during probe mode operation, do not use the boundary scan timings (t 55-58 ). 8. frcmc# should be tied to v cc (high) to ensure proper operation of the pentium processor as a primary processor. 9. setup time is required to guarantee recognition on a specific clock. the pentium processor must meet this specification for dual processor operation for the flush# and reset signals. 10.hold time is required to guarantee recognition on a specific clock. the pentium processor must meet this specification for dual processor operation for the flush# and reset signals. 11.to guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. 12.this input may be driven asynchronously. however, when operating two processors in dual processing mode, flush# and reset must be asserted synchronously to both processors. 13.when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be deasserted (inactive) for a minimum of two clocks before being returned active. 14.timings are valid only when dual processor is present. 15.maximum time dpen# is valid from rising edge of reset. 16.minimum time dpen# is valid after falling edge of reset. 17. the d/c#, m/io#, w/r#, cache#, and a31Ca5 signals are sampled only on the clk during which ads# is active. 18.bf and cputyp should be strapped to v cc or v ss . 19.reset is synchronous in dual processing mode and functional redundancy checking mode. all signals that have a setup or hold time with respect to a falling or rising edge of reset in up mode should be measured with respect to the first processor clock edge in which reset is sampled either active or inactive in dual processing and functional redundancy checking modes. 20.the phit# and phitm# signals operate at the core frequency. 21.these signals are measured on the rising edge of adjacent clks at 1.5 v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 22.in dual processing mode, timing t 14 is replaced by t 83a . timing t 14 is required for external snooping (e.g., address setup to the clk in which eads# is sampled active) in both uniprocessor and dual processor modes. 23.brdyc# and buschk# are used as reset configuration signals to select buffer size. 24.this assumes an external pullup resistor to v cc and a lumped capacitive load. the pullup resistor must be between 300 ohms and 1 kohms, the capacitance must be between 20 pf and 120 pf, and the rc product must be between 3 ns and 36 ns. v ol for picd1Cpicd0 is 0.55 v. 25.this is a flight time specification that includes both flight time and clock skew. the flight time is the time from when the unloaded driver crosses 1.5 v (50% of min. v cc ), to when the receiver crosses the 1.5 v level (50% of min. v cc ). see figure 13. 26.this is for the lock-step operation of the component only. this guarantees that apic interrupts will be recognized on specific clocks to support two processors running in a lock step fashion, including frc mode. frc on the apic pins is not supported but mismatches on these pins will result in a mismatch on other pins of the cpu. 27.the clk to picclk ratio for lock-step operation must be an integer and the ratio (clk/picclk) cannot be smaller than 4:1.
embedded pentium ? processor 38 datasheet figure 6. clock waveform figure 7. valid delay timings figure 8. float delay timings signal valid 1.5v 1.5v t max. x t min. x t x = t6, t8, t9, t10, t11, t12, t60i, t80a, t89
embedded pentium ? processor datasheet 39 figure 9. setup and hold timings figure 10. reset and configuration timings
embedded pentium ? processor 40 datasheet figure 11. test timings figure 12. test reset timings
embedded pentium ? processor datasheet 41 figure 13. 50% v cc measurement of flight time

▲Up To Search▲

Price & Availability of EMBEDDEDPENTIUM100

	To Download EMBEDDEDPENTIUM100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .